1. Field of the Invention
The present invention relates to the area of memory controller, more particularly, related to a double data rate (DDR) synchronous dynamic random access memory (SDRAM) controller.
2. Description of Related Art
DDR SDRAM (called as DDR memory herein) as a high-capacity, high-density and high-speed memory has been widely used in various chips. Main difference between the DDR memory and a previous generation SDRAM (called as SDRAM herein) is that the DDR memory can transfer data at the rising and falling edge of the clock, but the SDRAM only can transfer data at the rising edge of the clock. Furthermore, a clock frequency of the DDR memory is from 133 MHz to 200 MHz, but a clock frequency of the SDRAM is lower than 133 MHz.
High-speed clock and faster data transfer rate make a DDR memory controller more difficult in design. A delay difference of a data strobe signal DQS of the DDR memory relative to a clock signal DCLK of the DDR memory controller may be more than 5 ns when the DDR memory works at a maximum working temperature (125 degree Celsius) and a minimum working temperature (−40 degree Celsius) respectively.
FIG. 1 is a circuit diagram schematically showing a conventional DDR memory controller connected with a DDR memory.
The DDR memory controller includes a number of IO ports. Each IO port has a tri-state terminal PAD interacting with the DDR memory. When the IO port is used as an output port, an input signal of a terminal I of the IO port is outputted via the tri-state terminal PAD. When the IO port is used as an input port, an output signal of a terminal C of the IO port is inputted from the tri-state terminal PAD. The DDR memory controller includes a pair of edge triggers (e.g. D flip-flops) DFF1 and DFF2 and an inverter INV. Each edge trigger has a clock terminal CK, an input terminal D and an output terminal Q.
A clock signal DCLK of the DDR memory controller is provided to the inverter INV that inverts the clock signal DCLK and outputs an inverted clock signal INV_DCLK to the terminal I of the IO port IO1. The IO port IO1 outputs the inverted clock signal INV_DCLK to a clock terminal CK of the DDR memory via the tri-state terminal PAD thereof.
A data strobe terminal DQS of the DDR memory is coupled to the tri-state terminal PAD of the IO port IO3. The terminal C of the IO port IO3 is coupled to the clock terminal CK of the edge trigger DFF1. A data terminal DQn of the DDR memory is couple to the tri-state terminal PAD of the IO port IO2. The terminal C of the IO port IO2 is coupled to the input terminal D of the edge trigger DFF1. The edge trigger DFF1 is provided to sample the read data DQn on the falling edge and/or the rising edge of the data strobe DQS′ inputted from the data strobe terminal DQS and output the sampled read data DQ_S1 via the output terminal Q thereof.
The clock terminal CK of the edge trigger DFF2 is coupled to the clock signal DCLK of the DDR memory controller, and the input terminal D of the edge trigger DFF2 is couple to the output terminal Q of the edge trigger DFF1. The edge trigger DFF2 is provided to sample the read data DQ_S1 on the falling edge and/or the rising edge of the clock signal DCLK and output the sampled read data DQ_S2 via the output terminal Q thereof.
It can be seen that the read data DQ_S1 is obtained by using the data strobe DQS′ as the sampling clock, and the data DQ_S2 is obtained by sampling the read data DQ_S1 according to the clock signal DCLK. The delay of the clock signal DQS′ relative to the clock signal DCLK is caused by:
an output delay Tpat_out of the IO port, which is often 4.5 ns at the maximum working temperature and 2.5 ns at the minimum working temperature;
an accessing time Tac of the DDR memory, which is often 5 ns at the maximum working temperature and 2 ns at the minimum working temperature;
an input delay Tpat_in of the IO port, which is often 2.5 ns at the maximum working temperature and 1.5 ns at the minimum working temperature; and
an inverting delay TINV of the inverter INV, which is half of cycle of the clock signal.
The above delays are taken as examples for explanation and not all delays are taken into consideration. In practice, other factors may also affect the delay of the data strobe DQS′ relative to the clock signal DCLK. Hence, a certain design margin should be considered.
It is assumed that the clock frequency of the clock signal DCLK is 166 MHz, the delay of the data strobe DQS′ relative to the clock signal DCLK is about 15 ns at the maximum working temperature, and the delay of the clock signal DQS′ relative to the clock signal DCLK is about 9 ns at the maximum working temperature. The delay difference of the data strobe DQS′ relative to the clock signal DCLK of the DDR memory controller may be more than 6 ns at the maximum working temperature and the minimum working temperature. As a result, the DDR memory controller obtains the valid read data DQ_S2 in the difference clock cycles at the maximum working temperature and the minimum working temperature. It has to employ extra software to control the data read operation of the DDR memory controller according to a current working temperature. Thus, a burden of center processing unit is increased, an extra temperature detector is needed, and a reliability of read data is reduced.
Thus, improved techniques for memory controller are desired to overcome the above disadvantages.